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authorRaul E Rangel <rrangel@chromium.org>2019-04-23 16:02:15 -0600
committerMartin Roth <martinroth@google.com>2019-05-15 16:01:48 +0000
commit29150c83df8630a817e81eef593dd93fdb37b09f (patch)
tree7b096a18165fc0723470c1e069cbe9b5e3436a7a /util
parentcd51d7ced5a4996253c6dfc816ab7ef82533b2da (diff)
soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller
We need to support entering D3Cold from the OS to work around a bug in the SDHC where the data lines get stuck always reading zeros. BUG=b:122749418 TEST=Verified the linux kernel can transition between D3 and D0. Also verified that the device can suspend and resume and continue to have a functioning SD controller after. Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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