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| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-10 13:57:07 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-16 23:29:56 +0000 |
| commit | b27aa82a50cde46d43ea0dd6ad797eb9c248e6c8 (patch) | |
| tree | 314c8bcf0ec0ce4c02997dabf9d3a98d94f87ed0 /util/xcompile | |
| parent | f710955b93dddb094b9dacf651fe8a0730b21500 (diff) | |
soc/intel/skylake: Add proper support to enable UART2 in 16550 mode
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/xcompile')
0 files changed, 0 insertions, 0 deletions