soc/intel/common/block: Fix SATA chipset register definitions anomalies

SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.

Add new Kconfig option to address this delta between different PCH.

Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions