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authorSubrata Banik <subratabanik@google.com>2023-04-28 00:52:23 +0530
committerSubrata Banik <subratabanik@google.com>2023-05-06 05:36:44 +0000
commit792ce8197355d01093c26335906bec8c5e7a2761 (patch)
tree4d1d081ccc7bb3ddfdd9de5663cefb7f58675f1b /util/vgabios/pci-userspace.c
parent199728b4d2aade12c649e6a07579436ec36ca623 (diff)
soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise
This patch makes CSE sync in romstage default enabled unless ramstage config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it. TEST=Able to build google/marasov with this change where CSE sync is performed early inside romstage. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'util/vgabios/pci-userspace.c')
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