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authorAamir Bohra <aamir.bohra@intel.com>2020-09-09 14:34:36 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-10-12 08:52:12 +0000
commit7a04d05f1d54f93ae8d4d7b53eb5c1119446da49 (patch)
tree8d58912b24225531e777559579dfaecee37e647b /util/vgabios/device.c
parente9984c8e4fec24c2fe6320b2b6726f13ed7d7296 (diff)
mb/google/dedede: Enable SaGv support
Allow MRC training in SaGv low, mid and high frequencies. TEST=Verify memory trains at low, mid and high SaGv point through FSP debug logs enabled. Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/vgabios/device.c')
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