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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-03-20 10:58:51 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-23 19:30:49 +0000 |
| commit | c632bda2f6fe9dad5da4118ea9bb762a8eff1583 (patch) | |
| tree | f42a6bbad156a9e43b40960cb58e4d7de7365a5d /util/supermicro | |
| parent | 4629830b73d331d2130e6bf3e49acd24f2bab3f2 (diff) | |
soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE
According to the latest Tigerlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 256KiB. Change
DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined
empirically). JSL requires 192KiB.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'util/supermicro')
0 files changed, 0 insertions, 0 deletions