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| author | Duncan Laurie <dlaurie@google.com> | 2018-12-08 11:58:32 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-10 08:53:16 +0000 |
| commit | f63c3f6448ccff7236fa121308a3efb337245e27 (patch) | |
| tree | b5979b5d337e65239a0f0212748e24dd1228e3ac /util/superiotool/pci.c | |
| parent | c81f0b6433d971e0e2012e1b4cd363e0799bc6d5 (diff) | |
soc/intel/cannonlake: Fix GPIO reporting
The kernel GPIO driver only expects some GPIO communities to be exported
in the _CRS and it will not work correctly if the other communities are
exported.
CNL-LP: GPIO communities 0, 1, 4
CNL-H: GPIO communities 0, 1, 3, 4
Additionally one of the pin offset values was incorrect in GPIO
community 1 for CNL-LP. This doesn't have any specific failure mode but
it was found when auditing the GPIO code.
Details of the kernel expected map can be found in the linux kernel at
drivers/pinctrl/intel/pinctrl-cannonlake.c
BUG=b:120686247
TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that
pins >= 198 are not reading all zeros for the pin config registers.
Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'util/superiotool/pci.c')
0 files changed, 0 insertions, 0 deletions