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authorLijian Zhao <lijian.zhao@intel.com>2018-02-08 16:58:47 -0800
committerAaron Durbin <adurbin@chromium.org>2018-02-16 04:35:43 +0000
commite1b8221498b6742cd87271d736ffc6f8f0f82633 (patch)
tree1b3b00c8c8acdb5e298dcdc8c303f9faaa21bdce /util/superiotool/pci.c
parent20123a8838e5c8cdf002237dcf68aa048dc2161b (diff)
soc/intel/cannonlake: Update GPIO ASL
GPIO pin definition had been updated to match Cannonlake PCH-LP EDS, hence the ACPI dsdt table will include those changes as well. BUG=None TEST=Build coreboot image, flah coreboot image into DUT, and target system can boot up into OS. Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/superiotool/pci.c')
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