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authorJulien Viard de Galbert <jviarddegalbert@online.net>2018-03-05 11:10:16 +0100
committerNico Huber <nico.h@gmx.de>2018-03-09 12:57:54 +0000
commit546923f906308a737d7797cb96f183a121ab4e10 (patch)
tree333feac6b65abce3b0bf7571b73ab8f4d3cb11d5 /util/superiotool/ite.c
parent7b37668650f8ee13ace646dc98584074992a696f (diff)
soc/intel/denverton_ns: Update UART legacy mode to keep FSP traces
The FSP can only output its traces when the HSUART PCI device is available. - Move the hiding to after last FSP call. - Adapt coreboot PCI enumeration to keep the legacy configuration. With UART configured as legacy Linux will not re-enumerate it but detects it as legacy (ttyS0 instead of ttyS4). Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util/superiotool/ite.c')
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