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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-01-26 00:19:58 +1100
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-01-27 01:21:22 +0100
commit5b5f834e8475fc89af85d2d706b8c31f32e6f4f3 (patch)
tree1020239d1204322f0a765cffaf283ef93f609184 /util/superiotool/fintek.c
parent962b6c0a5e844e919ef0c28fee102f63fa8d5de9 (diff)
util/superiotool: Add initial support for Fintek F71869AD.
Change-Id: Ia2ce8214d8b419d0ca0186e6f6b2241097b0847b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4802 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'util/superiotool/fintek.c')
-rw-r--r--util/superiotool/fintek.c42
1 files changed, 42 insertions, 0 deletions
diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c
index 6ba962a105..aba0353a6b 100644
--- a/util/superiotool/fintek.c
+++ b/util/superiotool/fintek.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
* Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -76,6 +77,47 @@ static const struct superio_registers reg_table[] = {
{0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT},
{0x00,0x00,NANA,0x06,0x1c,0x01,EOT}},
{EOT}}},
+ {0x0710, "F71869AD", {
+ /* We assume reserved bits are read as 0. */
+ {NOLDN, NULL,
+ {0x02,0x07,0x20,0x21,0x25,0x26,0x27,0x28,0x29,0x2a,
+ 0x2b,0x2c,0x2d,EOT},
+ {0x00,0x00,0x08,0x14,0x00,0x00,MISC,0x38,0x6f,0x07,
+ 0x0f,0x00,0x28,EOT}},
+ {0x0, "Floppy",
+ {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
+ {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
+ {0x1, "COM1",
+ {0x30,0x60,0x61,0x70,0xf0,EOT},
+ {0x01,0x03,0xf8,0x04,0x00,EOT}},
+ {0x2, "COM2",
+ {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+ {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
+ {0x3, "Parallel port",
+ {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+ {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
+ {0x4, "Hardware monitor",
+ {0x30,0x60,0x61,0x70,EOT},
+ {0x01,0x02,0x95,0x00,EOT}},
+ {0x5, "Keyboard",
+ {0x30,0x60,0x61,0x70,0x72,0xf0,0xfe,0xff,EOT},
+ {0x01,0x00,0x60,0x01,0x0c,0x83,0x81,0x29,EOT}},
+ {0x6, "GPIO",
+ {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,0xe0,0xe1,
+ 0xe2,0xe3,0xe4,0xe5,0xe6,0xd0,0xd1,0xd2,0xd3,0xc0,
+ 0xc1,0xc2,0xb0,0xb1,0xb2,0xb3,0xa0,0xa1,0xa2,0xa3,
+ 0x90,0x91,0x92,0x93,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x3f,NANA,0x00,0x00,0xff,
+ NANA,0x00,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0x00,
+ 0xff,NANA,0x00,0x0f,NANA,0x00,0x00,0x1f,NANA,0x00,
+ 0x00,0x3f,NANA,0x00,EOT}},
+ {0x7, "BSEL",
+ {0x30,0x60,0x61,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT},
+ {0x00,0x00,0x00,0x01,0x00,0x00,NANA,0x00,0x0a,0x00,EOT}},
+ {0xa, "PME, ACPI",
+ {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfe,0xff,EOT},
+ {0x00,0x00,0x00,NANA,NANA,0x06,0x1c,0x1f,0x86,0x00,0x00,0x00,0x00,EOT}},
+ {EOT}}},
{0x2307, "F71889", {
/* We assume reserved bits are read as 0. */
{NOLDN, NULL,