util/superiotool: Add support for Fintek F71808A

Default values taken from the datasheet and from the dump of
an uninitialized F71808A on a Sapphire Pure Platinum H61.

Both the control registers and the HWM configuration registers
are added.

Change-Id: Ia6e2a7c13a5086d19ebdb426f2f975b43220a273
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18562
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 111 insertions, 1 deletions

diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c
index 5a30652a42..74e7f761c9 100644
--- a/util/superiotool/fintek.c
+++ b/util/superiotool/fintek.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
  * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
  * Copyright (C) 2014 Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -74,6 +75,49 @@ static const struct superio_registers reg_table[] = {
 			{0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT},
 			{0x00,0x00,NANA,0x06,0x1c,0x01,EOT}},
 		{EOT}}},
+	{0x0110, "F71808A", {
+		/* We assume reserved bits are read as 0. */
+		{NOLDN, NULL,
+			{0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,
+			 0x29,0x2a,0x2b,0x2c,0x2d,EOT},
+			{0x00,0x00,0x10,0x01,0x19,0x34,0x00,0x00,MISC,0x00,
+			 0xc0,0x21,0x2f,0x5c,0x27,EOT}},
+		{0x1, "COM1",
+			{0x30,0x60,0x61,0x70,0xf0,EOT},
+			{0x01,0x03,0xf8,0x04,0x00,EOT}},
+		{0x4, "Hardware monitor",
+			{0x30,0x60,0x61,0x70,EOT},
+			{0x01,0x02,0x95,0x00,EOT}},
+		{0x5, "Keyboard",
+			{0x30,0x60,0x61,0x70,0x72,0xfe,0xff,EOT},
+			{0x01,0x00,0x60,0x01,0x0c,0x01,0x29,EOT}},
+		{0x6, "GPIO",
+			{0x70,0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xcb,0xcc,
+			 0xcd,0xce,0xcf,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6,
+			 0xd7,0xd8,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2,0xf3,
+			 EOT},
+			{0x00,0x00,0x3f,NANA,0x00,0x00,0x00,0x00,0x00,0x00,
+			 0x00,0xe0,0x40,0x00,0x00,NANA,0x00,0x00,0x00,0x00,
+			 0x00,0x00,0x00,0x1f,NANA,0x00,0x00,0xff,NANA,0x00,
+			 EOT}},
+		{0x7, "WDT",
+			{0x30,0x60,0x61,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,
+			EOT},
+			{0x00,0x00,0x00,0x03,NANA,NANA,NANA,0x00,0x0a,0x00,
+			EOT}},
+		{0x8, "CIR",
+			{0x30,0x60,0x61,0x70,0xf0,0xf1,0xf8,0xf9,0xfa,0xfb,
+			 0xfc,0xfd,0xfe,EOT},
+			{0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x80,0x3b,
+			 0x00,0x00,0x00,EOT}},
+		{0xa, "PME, ACPI, and EUP Power Saving",
+			{0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
+			 0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,
+			 0xf6,0xf7,0xf8,0xf9,0xfa,0xfd,EOT},
+			{0x00,0x10,0xcc,0x0c,0x13,0x09,0xc7,0x09,0x63,0x00,
+			 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x3c,
+			 0x1f,0x00,0x00,0x00,0x00,NANA,EOT}},
+		{EOT}}},
 	{0x0710, "F71869A/AD", {
 		/* We assume reserved bits are read as 0. */
 		{NOLDN, NULL,
@@ -426,9 +470,64 @@ static const struct superio_registers reg_table[] = {
 	{EOT}
 };
 
+static const struct superio_registers hwm_table[] = {
+	{0x0110, "F71808A", {
+		{NOLDN, NULL,
+			{0x01, 0x02, 0x03, 0x08, 0x0a, 0x0b, 0x0c, 0x0d,
+			 0x0f,
+			 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
+			 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
+		      /* 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+			 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, */
+			 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+			 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
+			 0x60, 0x61, 0x62, 0x63, 0x64, 0x66, 0x6b, 0x6c,
+			 0x6d, 0x6f, 0x7f,
+			 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
+			 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e,
+			 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+			 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d,
+			 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x98,
+			 0x9b, 0x9c, 0x9e, 0x9f,
+			 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
+			 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
+			 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
+			 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
+			 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
+			 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
+			 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xec, 0xed, 0xee,
+			 0xef, EOT},
+			{0x03, 0x00, 0x01, 0x4c, 0x00, 0x00, 0x55, 0x00,
+			 0x20,
+			 NANA, NANA, NANA, NANA, RSVD, RSVD, RSVD, NANA,
+			 NANA, RSVD, RSVD, RSVD, RSVD, NANA, NANA, NANA,
+		      /* RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD,
+			 RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, */
+			 0x44, 0x00, NANA, 0x00, 0x00, 0x00, 0x00, 0x00,
+			 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x40,
+			 0x04, 0x00, 0x00,
+			 RSVD, RSVD, NANA, RSVD, NANA, RSVD, RSVD, RSVD,
+			 NANA, NANA, NANA, NANA, NANA, RSVD, RSVD,
+			 RSVD, RSVD, NANA, NANA, NANA, NANA, RSVD, RSVD,
+			 RSVD, RSVD, RSVD, RSVD, RSVD, RSVD,
+			 0x00, NANA, NANA, 0x00, 0x2e, 0xff, 0x05, 0x44,
+			 0x05, 0x55, 0x66, 0x00,
+			 0x03, 0xff, 0x00, 0x83, 0x03, 0xff, 0x3c, 0x32,
+			 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1d,
+			 0x0c, 0x25, 0x00, 0x80, 0x03, 0xff, 0x3c, 0x32,
+			 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1e,
+			 0x0f, 0xff, RSVD, 0x7f, RSVD, RSVD, RSVD, RSVD,
+			 RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x00,
+			 NANA, NANA, NANA, NANA, NANA, 0x00, 0x01, 0x01,
+			 0x00, EOT}},
+		{EOT}}},
+	{EOT}
+};
+
 void probe_idregs_fintek(uint16_t port)
 {
-	uint16_t vid, did;
+	uint16_t vid, did, hwmport;
 
 	probing_for("Fintek", "", port);
 
@@ -453,6 +552,17 @@ void probe_idregs_fintek(uint16_t port)
 
 	dump_superio("Fintek", reg_table, port, did, LDN_SEL);
 
+	if (extra_dump) {
+		regwrite(port, LDN_SEL, 0x04);	 /* Select LDN 4 (HWM). */
+
+		/* Get HWM base address (stored in LDN 4, index 0x60/0x61). */
+		hwmport = regval(port, 0x60) << 8;
+		hwmport |= regval(port, 0x61);
+
+		printf("Hardware monitor (0x%04x)\n", hwmport);
+		dump_superio("Fintek-HWM", hwm_table, hwmport, did, LDN_SEL);
+	}
+
 	exit_conf_mode_winbond_fintek_ite_8787(port);
 }