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authorUsha P <usha.p@intel.com>2019-11-28 10:05:45 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-12-26 10:44:17 +0000
commit33ff4cc137e501b14859bc67cc7e85dd60a863cc (patch)
tree213e74f46592f0a1c029667cb339c80b0561e9ba /util/superiotool/aspeed.c
parent5395123b849da143d9621b67a6837defe9501acf (diff)
soc/intel/cannonlake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBus init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot hatch successfully. Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'util/superiotool/aspeed.c')
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