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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-16 14:46:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-24 11:42:29 +0000 |
| commit | 3d35756d5a9ea48284c6a997e45d01e196bb6e48 (patch) | |
| tree | 1be88e5ea229699d15bcf62fa7602226a9bf498f /util/superiotool/amd.c | |
| parent | a8b82717ee1be13097487d0ed45699537dc67a78 (diff) | |
nb/intel/ironlake: Correct even more replay issues
The per-lane registers need to be modified in some cases. Also, MRC
does not have any delay after the loop, so remove it.
Tested on out-of-tree HP 630, still boots.
Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/superiotool/amd.c')
0 files changed, 0 insertions, 0 deletions