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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-02-03 13:28:46 +0530
committerMartin Roth <martinroth@google.com>2017-02-08 20:04:17 +0100
commit6ff7e8f550df1ef05e93546892888b66c132ae31 (patch)
tree8ef9be8ab6cda44a5c545ef53ad6b9a083dbf78a /util/superiotool/README
parent0254c2d99fc7a5858be4826c576ca743d005b213 (diff)
vendorcode/intel/skykabylake: Update CpuConfigFspData.h file
The FSP UPD offsets and the corresponding structure size do not match, CpuConfigData.h needs an update to align the same. Hence update the header file based on FSP version 1.4.0. BUG=chrome-os-partner:61548 BRANCH=none TEST=Built and booted KBLRVP and verify that all UPDs are in sync in both coreboot and FSP. Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18285 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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