soc/amd/mendocino: add and use missing cpu_vid_8 pstate_msr field

Mendocino uses the SVI3 standard for CPU core voltage control which uses
9 data bits instead of the 8 in the SVI2 case and also calculates the
actual voltages with a different formula. The Mendocino code uses the
correct formula since commit 8d2bfbce23f6 ("soc/amd/sabrina/acpi:
Correct VID decoding on Sabrina"), but the MSR definition in the PPR
hasn't been updated to show the additional bit. The definition of the
register that is mirrored by these MSRs descries this 9th CPU voltage ID
bit though. Since this bit is expected to be zero, this shouldn't cause
a change in behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I05acd239300836a34e40cd3f31ea819b79766e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73969
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

0 files changed, 0 insertions, 0 deletions