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authorZhiqiang Ma <zhiqiang.ma@mediatek.com>2021-06-03 09:41:47 +0800
committerHung-Te Lin <hungte@chromium.org>2021-06-05 13:05:15 +0000
commit1c70f8f48aa067e2718b36978ebf2b046508e7a1 (patch)
treea2aeb1533c254a3187c47583611bcdf44c53ef0e /util/scripts/no-fsf-addresses.sh
parentef53634d9a68c93b123f792dc4a0336346b82b8c (diff)
soc/mediatek/mt8195: fix GPIO register offsets
Correct the offsets by MT8195 Register Map V0.2-1 chapter: 3.2 GPIO Controller (page 3272) Control register names: PUPD_CFG0 PU_CFG0 Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55163 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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