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authorArthur Heymans <arthur@aheymans.xyz>2018-04-09 22:10:33 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-07 06:42:14 +0000
commit4bdfebd4d88c1d84662cae3d11de1ee40f9e0017 (patch)
tree561e703f590100dcdd93b3f9cb55825235636cc4 /util/scripts/gerrit-rebase
parente07df9d78351cda0818309fc7f3e78d8057d421e (diff)
nb/intel/pineview: Enable and allocate 8M for TSEG
TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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