sc7180: clock: Fix QUP DFSR configuration for perf levels

Update the QUP DFSR cmd to clear the SW control and also update the perf
registers when M is set. While at it also update the d_2 values.

Tested: validated DFSR clock configuration and M/N/D values.

Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

0 files changed, 0 insertions, 0 deletions