diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-09-13 13:35:34 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-30 13:37:57 +0000 |
| commit | f3c42825f3d984ff6246789167a527ad51b6d094 (patch) | |
| tree | b00d615606d5fa330ef2d6c340ae3d4f7ab545b4 /util/sconfig/sconfig.tab.h_shipped | |
| parent | 4df35b6ec88be35a946565438a4c5c51fc3ad3b9 (diff) | |
soc/intel/alderlake: Add CPU ID 0x906a4
TEST=Build and boot brya
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I4342c7343876eb40c2955f6f4dd99d6346852dc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Diffstat (limited to 'util/sconfig/sconfig.tab.h_shipped')
0 files changed, 0 insertions, 0 deletions