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| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-25 21:34:42 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:46 +0200 |
| commit | 8ef55ee9969de3003eae9e3113b7497799ba14ec (patch) | |
| tree | 5b4103c250ddbaf1b15d636072d9b9a11f741c58 /util/romcc | |
| parent | 87d4a201aba0cb1c422546a42fdc7e9b10c61fdb (diff) | |
Broadwell: Revise programming flow for write-once registers
Extended PCIe Capability and Advanced Error Report locates at
offset 0x100 is W/O, and the subsequent write following the 1st
write to the register takes no effect.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9
Original-BUG=chrome-os-partner:31424.
Original-TEST=Build a image and check the programming value is correct on
Original-Samus.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db
Original-Reviewed-on: https://chromium-review.googlesource.com/219985
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844
Reviewed-on: http://review.coreboot.org/9209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'util/romcc')
0 files changed, 0 insertions, 0 deletions