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authorAaron Durbin <adurbin@chromium.org>2016-03-18 11:19:38 -0500
committerAaron Durbin <adurbin@chromium.org>2016-03-23 14:24:44 +0100
commiteebe0e0db14476dde980896b8eb8a97129436af3 (patch)
tree9a42d31c63f9aa0ead4c466d22a690e1406336cb /util/romcc
parent7f8afe063139f6fc7076a3e4edf6093a953792dc (diff)
soc/intel/apollolake: utilize postcar phase/stage
The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstrap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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