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authorAaron Durbin <adurbin@chromium.org>2018-01-23 10:53:05 -0700
committerMartin Roth <martinroth@google.com>2018-01-24 16:27:03 +0000
commit24079323d4d83db4ce0ff0646309bd644b53aa76 (patch)
tree9f77bd4d4bb399ad895016c24bdb78e90b6e2383 /util/romcc
parent137484dee70b378ee557de4e6bbe59716e4791f0 (diff)
soc/amd/stoneyridge: provide alternate monotonic timer
The TSC has been observed to be ticking at a non-constant rate in early boot. The root cause is still not known, but this misbehavior necessitates an alternative monotonic timer source. Use the perf TSC which ticks at 100 MHz. This also means the timestamp table is not accurate as well. Root cause of TSC rate instability needs to be resolved in order to fix that. BUG=b:72170796 Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'util/romcc')
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