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authorUwe Poeche <uwe.poeche@siemens.com>2019-07-09 14:32:43 +0200
committerMartin Roth <martinroth@google.com>2019-07-23 15:49:09 +0000
commit868c8074b585e8465c315b0fbcafb940eaec27b7 (patch)
treeae74ee7616e78891679b9c4988bf224efd7e1386 /util/romcc
parent7724cebf978a17f0a2c6117dfebc71d56723d53a (diff)
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary. tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s. Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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