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authorEric Biederman <ebiederm@xmission.com>2003-06-19 15:14:52 +0000
committerEric Biederman <ebiederm@xmission.com>2003-06-19 15:14:52 +0000
commitf7a0ba84dcddf08cdd6a4431c899ae1ee0ed986c (patch)
tree534aa45bab630b970d02f2f7f514dc3acc9d9683 /util/romcc/tests
parent9dbd46077615b14f28f6a6b398c392f608af68e1 (diff)
- Update the romcc version.
- Add an additional consistency check to romcc and fix the more obvious problems it has uncovered With this update there are no known silent failures in romcc. - Update the memory initialization code to setup all 3 of the memory sizing registers properly - In auto.c test our dynamic maximum amount of ram. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/romcc/tests')
-rw-r--r--util/romcc/tests/simple_test34.c71
-rw-r--r--util/romcc/tests/simple_test35.c9
-rw-r--r--util/romcc/tests/simple_test36.c41
-rw-r--r--util/romcc/tests/simple_test37.c10
4 files changed, 131 insertions, 0 deletions
diff --git a/util/romcc/tests/simple_test34.c b/util/romcc/tests/simple_test34.c
new file mode 100644
index 0000000000..3c2b606fc2
--- /dev/null
+++ b/util/romcc/tests/simple_test34.c
@@ -0,0 +1,71 @@
+
+typedef __builtin_msr_t msr_t;
+
+static msr_t rdmsr(unsigned long index)
+{
+ return __builtin_rdmsr(index);
+}
+
+static void uart_tx_byte(unsigned char data)
+{
+ while(!(__builtin_inb(0x3f8 + 0x05) & 0x20))
+ ;
+ __builtin_outb(data, 0x3f8 + 0x00);
+
+ while(!(__builtin_inb(0x3f8 + 0x05) & 0x40))
+ ;
+}
+
+
+static void print_nibble(unsigned nibble)
+{
+ unsigned char digit;
+ digit = nibble + '0';
+ if (digit > '9') {
+ digit += 39;
+ }
+ uart_tx_byte(digit);
+}
+
+static void print_debug_hex32(unsigned int value)
+{
+ print_nibble((value >> 28U) & 0x0fU);
+ print_nibble((value >> 24U) & 0x0fU);
+ print_nibble((value >> 20U) & 0x0fU);
+ print_nibble((value >> 16U) & 0x0fU);
+ print_nibble((value >> 12U) & 0x0fU);
+ print_nibble((value >> 8U) & 0x0fU);
+ print_nibble((value >> 4U) & 0x0fU);
+ print_nibble(value & 0x0fU);
+}
+
+static void print_debug(const char *str)
+{
+ unsigned char ch;
+ while((ch = *str++) != '\0') {
+ uart_tx_byte(ch);
+ }
+}
+
+static void main(void)
+{
+ unsigned long start, stop;
+ msr_t msr;
+ msr = rdmsr(0xC001001A);
+ print_debug("TOP_MEM: ");
+ print_debug_hex32(msr.hi);
+ print_debug_hex32(msr.lo);
+ print_debug("\r\n");
+
+ start = 0;
+ stop = msr.lo;
+ print_debug("Testing DRAM : ");
+ print_debug_hex32(start);
+ print_debug("-");
+ print_debug_hex32(stop);
+ print_debug("\r\n");
+
+ print_debug("DRAM verify: ");
+ print_debug_hex32(start);
+ print_debug_hex32(stop);
+}
diff --git a/util/romcc/tests/simple_test35.c b/util/romcc/tests/simple_test35.c
new file mode 100644
index 0000000000..d60b157f25
--- /dev/null
+++ b/util/romcc/tests/simple_test35.c
@@ -0,0 +1,9 @@
+static void main(void)
+{
+ __builtin_msr_t msr;
+ msr = __builtin_rdmsr(0xC001001A);
+ while(__builtin_inb(0x3fd))
+ ;
+ __builtin_outb(msr.hi, 0x3f8);
+
+}
diff --git a/util/romcc/tests/simple_test36.c b/util/romcc/tests/simple_test36.c
new file mode 100644
index 0000000000..9044bda7b9
--- /dev/null
+++ b/util/romcc/tests/simple_test36.c
@@ -0,0 +1,41 @@
+static void order_dimms(void)
+{
+ unsigned long tom;
+
+ tom = 0;
+ for(;;) {
+
+ unsigned csbase, csmask;
+ unsigned size;
+ unsigned index;
+ csbase = 0;
+
+ for(index = 0; index < 1; index++) {
+ csbase = __builtin_inl(0x40);
+ }
+ if (csbase == 0) {
+ break;
+ }
+
+
+ size = csbase;
+
+ csbase = (tom << 21);
+
+ tom += size;
+
+
+ csmask = size;
+ csmask |= 0xfe00;
+
+
+ __builtin_outl(csbase, 0xCFC);
+
+ __builtin_outl(0xc260, 0xCF8);
+ __builtin_outl(csmask, 0xCFC);
+ }
+
+ tom &= ~0xff000000;
+
+ __builtin_outl(tom, 0x1234);
+}
diff --git a/util/romcc/tests/simple_test37.c b/util/romcc/tests/simple_test37.c
new file mode 100644
index 0000000000..85c622b17d
--- /dev/null
+++ b/util/romcc/tests/simple_test37.c
@@ -0,0 +1,10 @@
+static void main(void)
+{
+ unsigned csbase, csmask;
+
+ csbase = 0x40;
+ csmask = 0xfe00;
+
+ __builtin_outl(csbase, 0x40);
+ __builtin_outl(csmask, 0x60);
+}