diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2019-07-23 22:02:16 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-31 04:27:48 +0000 |
| commit | 810527a4eacedfb4d63dd90d413be53c9119d024 (patch) | |
| tree | c9611e1f42ec82d9f00852a2582be36e1dfa0313 /util/romcc/tests/simple_test4.c | |
| parent | 047cac7b42eaf5b799e653ed1cc4a1b13e3f95e4 (diff) | |
soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix
Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.
Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/romcc/tests/simple_test4.c')
0 files changed, 0 insertions, 0 deletions