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| author | Sean Rhodes <sean@starlabs.systems> | 2022-07-27 15:23:37 +0100 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-17 19:48:11 +0000 |
| commit | b660f4ee47ac2eab478a541af5f0e9217236ae22 (patch) | |
| tree | 0d6d7aad643313eac9b5a37bba5bd139b8772595 /util/riscv | |
| parent | acb4d72fff2f67e182d8fb0354fa269d26800b76 (diff) | |
soc/intel/apollolake: Enable DPTF & SMBus as it is a required device
coreboot is unable to disable certain devices, whilst many are hidden
DPTF and SMBus are not. Set this to enabled chipset so that it is
enabled by default.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I85d74179b6fe3c6126566422f82f7b806f80d0c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions