diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2019-07-26 00:03:29 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-09 01:32:53 +0000 |
| commit | ca38fbcdbfcb5024496d2577f71de06745c22aeb (patch) | |
| tree | bbd0412ece808ce427b48ac0bf31fdc552db26a8 /util/riscv | |
| parent | dacd5b9a6ad7d4273af83d356dc869660a04662e (diff) | |
mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions