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| author | Keith Hui <buurin@gmail.com> | 2020-05-05 21:52:35 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-06 07:10:13 +0000 |
| commit | e22c597bf64413ee4329c8869484d8a1f290f217 (patch) | |
| tree | cb69809b06f7682100d1d3b018c3b1fa40e6077d /util/riscv | |
| parent | 6462cbb2c20bae0cf309a3eb4ce70adff573e75a (diff) | |
sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtime
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff)
moved the southbridge ACPI stuff to its own file. It also
(prematurely) listed PM and SMBus I/O port ranges as a #defined
fixed value.
Since these two ranges are not expected to change at runtime anyway,
we can simply drop the ASL code doing the read.
Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions