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| author | Angel Pons <th3fanbus@gmail.com> | 2022-02-13 13:35:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 16:19:37 +0000 |
| commit | d85319a12d6bf4341c46bf83cd2f8ce1cc1ba3e0 (patch) | |
| tree | 80f4b842236b9c7d084210393a9e66279d1f8d2f /util/riscv | |
| parent | dfde9b125ccf0e044cec68cbaa7bd1a3fa8a8920 (diff) | |
soc/intel/common/block/pcie/rtd3: Fix bit checks
Fix always-true conditions to properly test whether a bit is set.
Change-Id: Ibfeafe222c0c2b39ced5b77f79ceb0c679a471b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions