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| author | Christian Walter <christian.walter@9elements.com> | 2020-04-27 18:11:51 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2020-05-04 14:20:17 +0000 |
| commit | e01054d86eecfff846764e640eaafe58b5d5fb5d (patch) | |
| tree | 443a196cd883e6b8e89b947f612fdcabda56fd94 /util/riscv | |
| parent | 066007590f5b904962f9965ace5485ddab7a89c3 (diff) | |
soc/intel/cannonlake: Add DisableHeciRetry to config
Add DisableHeciRetry to the chip config and parse it in romstage.
Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions