diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-28 22:06:37 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-01 19:55:03 +0000 |
| commit | 1ab6f0c176c1aa6947bf0d3fbe0a213f316e9c67 (patch) | |
| tree | 79b610c87ced9a8f46b705dab031521cdef2e3df /util/riscv | |
| parent | e7601b5d6c6c3a0fdf0d779cfe12b9a381f0fba4 (diff) | |
soc/intel/tigerlake: Configure TCSS xHCI and xDCI
Configure xHCI, xDCI according to board design
BUG=none
BRANCH=none
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions