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author | Vinod Polimera <vpolimer@codeaurora.org> | 2020-03-03 12:13:26 +0530 |
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committer | Julius Werner <jwerner@chromium.org> | 2020-09-10 00:25:26 +0000 |
commit | 3b4c45efa264ab68512eeca0dc5b9d65283dd8bc (patch) | |
tree | 7c68903b26918ae228ef0bb0d0fa53ad23d8cfcc /util/riscv | |
parent | c4e0b0a31378ae164ae2b6988c9779d96b627e84 (diff) |
sc7180: Add display hardware pipe line initialization
Add sc7180 display hardware pipeline programming support
and invoke the display initialization from soc_init.
Changes in V1:
- added display init required check.
- added edid read function using i2c communication.
- added sn65dsi86 bridge driver to init bridge.
- moved display initialization to mainboard file.
Changes in V2:
- moved diplay init sequence to mainboard file
- moved edid read function to bridge driver.
- calculated timing paramters using edid parameters.
- removed command mode config code.
- moved bridge driver to drivers/ti.
- seperated out bridge and soc code with mainboard file as interface.
Changes in V3:
- add GPIO selection at runtime based on boardid.
- add vbif register struct overlay.
Changes in V4:
- update gpio config for lazor board.
Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions