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author | Felix Held <felix-coreboot@felixheld.de> | 2024-08-02 02:11:24 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-05 13:09:02 +0000 |
commit | 97e8ef4c708f5c19d6e58d42db01d685829e4ce1 (patch) | |
tree | 208c3946737c58cb5c75216ad7b69efcd6e64b79 /util/riscv/sifive-gpt.py | |
parent | 5f3dd1cfed23cc8997b9b6235162a8aca8a573fd (diff) |
soc/amd: add PSP SMI handler stub
The PSP can send SMIs to the x86 side to have the SMI handler service
requests from the PSP. This commit adds an empty PSP SMI handler; the
actual implementation is added in later patches to keep the patches
relatively small.
This patch is a slightly modified version of parts of CB:65523.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83739
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/riscv/sifive-gpt.py')
0 files changed, 0 insertions, 0 deletions