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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 17:18:46 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:14:03 +0000 |
| commit | 4f86d630066eea380be76952f533ddaa5a8b28fd (patch) | |
| tree | 749a7bd207feed0da8d2da200d05adb324e0e2e5 /util/riscv/sifive-gpt.py | |
| parent | 2921cbf277f533126e1bd84702e83957c977f5b6 (diff) | |
nb/intel/sandybridge: Clean up COMPOFST1 logic
This register needs to be updated differently depending on the CPU
generation and stepping. Handle this as per reference code. Further,
introduce a bitfield for the register to make the code easier to read.
Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'util/riscv/sifive-gpt.py')
0 files changed, 0 insertions, 0 deletions