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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-12 23:50:37 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-14 18:54:35 +0000 |
| commit | c66e1c2a319a682a4616589901df301a816076ae (patch) | |
| tree | 9d05943ffb743a0a31f15e65c60efe6ab52d6481 /util/riscv/description.md | |
| parent | ed21df6cec49f2c7dd5ae8286eaee958104e781d (diff) | |
soc/intel/cnl: enable ACPI CPPC entries generation
Enable CPPC entries generation, needed for Intel SpeedShift.
Test: dumped SSDT from Clevo L140CU and checked decompiled version
Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/riscv/description.md')
0 files changed, 0 insertions, 0 deletions