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| author | Deepti Deshatty <deepti.deshatty@intel.com> | 2021-05-12 16:09:07 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-14 08:57:57 +0000 |
| commit | 8386e7cd5bf763c281c0b25e6de127c289766de5 (patch) | |
| tree | 093bce18f5919e066d34c65ef7c6412861b1a3d3 /util/qualcomm/createxbl.py | |
| parent | f35be77ee36b7c591e28c905cd83acb6593f954a (diff) | |
soc/intel/alderlake: Add known CPU Port IDs for GPIO communities
Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/qualcomm/createxbl.py')
0 files changed, 0 insertions, 0 deletions