summaryrefslogtreecommitdiff
path: root/util/pgtblgen/description.md
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-10-21 18:47:46 +0200
committerNico Huber <nico.h@gmx.de>2019-11-10 22:57:29 +0000
commit8256ca0e14e57b17b27a81b16f220c94d728e117 (patch)
treeb1bf3a14aa5509c6105d7a7af09e7181f26a6b2b /util/pgtblgen/description.md
parent3c1e986119cdfece27e5bf953576fa01882bb773 (diff)
soc/intel/braswell: Update microcode before FSP
The google FSP Braswell version has broken microcode update code and FSP checks at some point if the installed microcode version is non zero, so coreboot has to update it before calling FSP-T. This is fixed with newer FSP releases by Intel, but doing updates in coreboot won't hurt. Tested with both Intel FSP and google FSP. Change-Id: I3e81329854e823dc66fec191adbed617bb37d649 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36198 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/pgtblgen/description.md')
0 files changed, 0 insertions, 0 deletions