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authordavid <david_wu@quantatw.com>2015-12-29 15:02:04 +0800
committerMartin Roth <martinroth@google.com>2016-02-09 19:44:57 +0100
commit4852dec1ab21e6c6e32eb85354ce4f4182537442 (patch)
tree42ae4e8c398d9f2ec7cdc9f3018c319e36acf655 /util/optionlist
parent1c85fea945307404546ac953a65329b2b37aec36 (diff)
intel/skylake: Add gpio macro for unused GPIO pins
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. BUG=none BRANCH=none TEST=Build and boot lars Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9 Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319964 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/13628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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