mainboard/google/zoombini: add ACPI entry for cr50

This adds coreboot device tree entries on zoombini & meowth for the
cr50.  Also, fixes the GPIO pin IRQ settings to be falling edge.  This
is based on what we do for fizz.

BUG=b:71722449
TEST=booted to linux on meowth: tpm_version command now sees the cr50.

localhost ~ # tpm_version
  TPM 2.0 Version Info:
  Chip Version:        2.0.0.0
  Spec Family:         322e3000
  Spec Family String:  2.0
  Spec Level:          0
  Spec Revision:       116
  Manufacturer Info:   43524f53
  Manufacturer String: CROS
  Vendor ID:           xCG fTPM
  TPM Model:           00000001
  Firmware Version:    0ad551830bcf7a82
localhost ~ # uname -a
Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux
localhost ~ #

and we see interrupts when talking to the cr50:

localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru
pts
 84:       4687   IO-APIC  84-edge      cr50_spi
  TPM 2.0 Version Info:
  Chip Version:        2.0.0.0
  Spec Family:         322e3000
  Spec Family String:  2.0
  Spec Level:          0
  Spec Revision:       116
  Manufacturer Info:   43524f53
  Manufacturer String: CROS
  Vendor ID:           xCG fTPM
  TPM Model:           00000001
  Firmware Version:    0ad551830bcf7a82
 84:       4799   IO-APIC  84-edge      cr50_spi
localhost ~ #

Change-Id: I9d503334502503ef49515e4a8736d967bc454a98
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

0 files changed, 0 insertions, 0 deletions