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authorFelix Held <felix-coreboot@felixheld.de>2023-03-06 23:31:40 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-08 12:00:11 +0000
commitd3b077e2b6329ea1d6e36d8abc56b8740a9e79d7 (patch)
treefb7eb741d1eb6324e944a537e82487a58ed8b5d7 /util/nvramtool/DISCLAIMER
parente930360bbe2239723ea9f7c493860053a069e71f (diff)
soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper
Introduce the get_cstate_info helper function that populates the caller- provided cstate_values array with the data returned by the SoC-specific get_cstate_config_data function. From the array get_cstate_config_data returns, only the ctype, latency and power fields are used, so the rest can be left uninitialized. Those 3 fields are compile-time constants. For each entry, write_cstate_entry will generate the corresponding resource information from the given data. In the C1 case where ctype is 1, the state is entered via a MWAIT instruction, while the higher C states are entered by doing an IO read from a specific IO address. This IO address is x - 1 bytes into the IO region starting at MSR_CSTATE_ADDRESS for the Cx state. So for example C2 is entered by reading from the C state IO base address + 1. This resource information is generated during runtime, since the contents of MSR_CSTATE_ADDRESS aren't necessarily known at compile-time. MAX_CSTATE_COUNT is introduced so that the caller can allocate and pass a buffer with space for the maximum number of C state entries. This maximum number corresponds to the number of IO addresses the CPU traps beginning from MSR_CSTATE_ADDRESS. In practice, it's unlikely that more than 3 or maybe 4 C states will be available though. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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