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authorMichał Żygowski <michal.zygowski@3mdeb.com>2023-10-16 15:32:59 +0200
committerMichał Żygowski <michal.zygowski@3mdeb.com>2023-10-19 09:44:32 +0000
commit7357f2a0ff13380410ff23da9ac0f8648e1319bf (patch)
treef7029fca17af399eee14a7eecd71d1af9a210123 /util/nvramtool/ChangeLog
parentfa78ecacec2694753068a9e769a3d68d5dad2b62 (diff)
soc/intel/alderlake: Fix incorrect microcode comments
The microcode for RPL-S C0 and H0 is actually available, however, the name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos in the comments. Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256 sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256 sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag microcode-20230808: 5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9 Update the comments to correctly indicate supported CPU steppings. Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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