diff options
| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2012-07-11 09:31:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-13 08:40:14 +0200 |
| commit | 42b808e889b32344977fa067120ea02fa803e9a4 (patch) | |
| tree | 26d2d84012827dde135e6483daa4457efe32a22f /util/msrtool | |
| parent | 0fa50a1990fcdfca6a9f75a68f8e4ed22ddd6949 (diff) | |
msrtool: add support for cs5536 LPC_SERIRQ (0x5140004e)
This register is helpful for porting new mainboards based on
cs5536 southbridge.
Change-Id: Iff3adc2c2fbc672c8541096756f95b3322f6ab19
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1211
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'util/msrtool')
| -rw-r--r-- | util/msrtool/cs5536.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/util/msrtool/cs5536.c b/util/msrtool/cs5536.c index b3f2e5d50d..666a93aa6b 100644 --- a/util/msrtool/cs5536.c +++ b/util/msrtool/cs5536.c @@ -1310,5 +1310,46 @@ const struct msrdef cs5536_msrs[] = { }}, { BITS_EOT } }}, + { 0x5140004e, MSRTYPE_RDWR, MSR2(0, 0), "LPC_SERIRQ", "LPC Serial IRQ Control", { + { 31, 16, "INVERT", "IRQ[x] input is active low", PRESENT_HEX }, + { 15, 8, RESERVED }, + { 7, 1, "SIRQ_EN", "Serial IRQ Enable", PRESENT_BIN, { + { MSR1(0), "Disable" }, + { MSR1(1), "Enable" }, + { BITVAL_EOT } + }}, + { 6, 1, "SIRQ_MODE", "Serial IRQ Interface Mode", PRESENT_BIN, { + { MSR1(0), "Continuous (Idle)" }, + { MSR1(1), "Quiet (Active)" }, + { BITVAL_EOT } + }}, + { 5, 4, "IRQ_FRAME", "IRQ Data Frames", PRESENT_BIN, { + { MSR1(0), "17" }, + { MSR1(1), "18" }, + { MSR1(2), "19" }, + { MSR1(3), "20" }, + { MSR1(4), "21" }, + { MSR1(5), "22" }, + { MSR1(6), "23" }, + { MSR1(7), "24" }, + { MSR1(8), "25" }, + { MSR1(9), "26" }, + { MSR1(10), "27" }, + { MSR1(11), "28" }, + { MSR1(12), "29" }, + { MSR1(13), "30" }, + { MSR1(14), "31" }, + { MSR1(15), "32" }, + { BITVAL_EOT } + }}, + { 1, 2, "START_FPW", "Start Frame Pulse Width", PRESENT_BIN, { + { MSR1(0), "4 clocks" }, + { MSR1(1), "6 clocks" }, + { MSR1(2), "8 clocks" }, + { MSR1(3), "Reserved" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, { MSR_EOT } }; |