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authorGabe Black <gabeblack@google.com>2013-06-18 06:08:42 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 22:32:00 +0200
commitc883fdc964207d3871e8609c67988c07d448a87d (patch)
treed9fb63c0cb91bc94b12ccce291d70f30ce46b97c /util/msrtool
parente6af9296619a8bc1abe0c19268c9d961bf73843f (diff)
exynox5420: Remove the 5250 clock registers and fix the SPI frequency.
The 5420 clock code still had a data structure in it for the 5250 clock registers which was used by some of the clock functions. That caused some clocks to be configured incorrectly, specifically the i2c clock which was running at about 80KHz instead of about 600KHz as configured by U-Boot. Also, the registers and bit positions used to set up the SPI bus were not consistent with U-Boot, and if the bus clock rate were set to 50MHz, a rate which has historically worked on snow, loading would fail. With these fixes the clock rate can be set to 50MHz and the device boots as much as is expected. I haven't yet measured the actual frequency of the bus to verify that it's now being calculated correctly. Change-Id: Id53448fcb6d186bddb3f889c84ba267135dfbc00 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3678 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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