soc/intel/cannonlake: provide LPDDR4 memory init

Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

0 files changed, 0 insertions, 0 deletions