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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-07-24 15:37:13 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-13 16:33:23 +0200 |
| commit | edf1cb78e29edd768ef9641093bb3eae3c8c91d7 (patch) | |
| tree | 88b958c35863fe243504820d31f152af948a80ee /util/msrtool/intel_pentium4_later.c | |
| parent | 4f7cf3a4466df8f84ef352d2d496a2e7a075ac13 (diff) | |
skylake: Add Deep Sx configuration for wake pins
Add support for enabling various pins in Deep Sx by setting
a register in the mainboard devicetree.
BUG=chrome-os-partner:43079
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'util/msrtool/intel_pentium4_later.c')
0 files changed, 0 insertions, 0 deletions