diff options
author | Nicholas Chin <nic.c3.14@gmail.com> | 2024-02-07 15:23:46 -0700 |
---|---|---|
committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-08-27 00:44:51 +0000 |
commit | 5c727355784b09787b69753d68683d81428df419 (patch) | |
tree | 828bc7befb0c58c1150fafc37d6e6f23037bfd4a /util/msrtool/intel_pentium3_early.c | |
parent | 7a2cde9cead809f00162f090d7b79befc000452c (diff) |
mb/dell: Add Latitude E6320 (Sandy Bridge)
Mainboard is PAL70/LA-6611P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A22 of the vendor firmware. This port has not been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82130
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/msrtool/intel_pentium3_early.c')
0 files changed, 0 insertions, 0 deletions