diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-23 18:16:26 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-28 14:19:13 +0000 |
| commit | 75db596654bb0f4847aa358727c90f31fbe5eb04 (patch) | |
| tree | c181bd52fe1ea131819a484a1c3ee4c4249252df /util/msrtool/intel_nehalem.c | |
| parent | 403458e7ec0fae1345cd82128b71d5ab0b66fd77 (diff) | |
util/msrtool: Fix typos
Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'util/msrtool/intel_nehalem.c')
| -rw-r--r-- | util/msrtool/intel_nehalem.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 11acdd80d0..726ad0a36c 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -307,7 +307,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { /* This bit enables a system executive to use - * VMX in conjuction with SMX to support Intel + * VMX in conjunction with SMX to support Intel * Trusted Execution Technology. */ { MSR1(0), "VMX inside of SMX operation disabled" }, @@ -1109,7 +1109,7 @@ const struct msrdef intel_nehalem_msrs[] = { /* Whole package bit */ { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "CPU switch to the Minimum Enhaced Intel \ + { MSR1(1), "CPU switch to the Minimum Enhanced Intel \ SpeedStep Technology operating point when all \ execution cores enter MWAIT (C1)" }, { BITVAL_EOT } @@ -1373,9 +1373,9 @@ const struct msrdef intel_nehalem_msrs[] = { /* if CPUID.0AH EAX[7:0] > 2 */ { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { @@ -1396,9 +1396,9 @@ const struct msrdef intel_nehalem_msrs[] = { /* if CPUID.0AH: EAX[7:0] > 2 */ { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { @@ -1419,9 +1419,9 @@ const struct msrdef intel_nehalem_msrs[] = { /* if CPUID.0AH: EAX[7:0] > 2 */ { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { |