diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-14 09:09:29 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-15 03:56:51 +0000 |
| commit | 15a971b89fe23eb92cd3a88bff8726beae87669d (patch) | |
| tree | fc66ffc3cf0dcb9b8084d32b457dddab8458fe3c /util/msrtool/intel_nehalem.c | |
| parent | 8b72aaf3f723c3be348879bb089cc741c4db73ad (diff) | |
util/msrtool: Fix swapped IA32_MC3_x and IA32_MC4_x
Registers IA32_MCi_xx are defined as architectural MSRs
since "P6 Family Processors" and should have model-agnostic
indexing.
Note that in IA32 architecture manual, names of these MSRs are
similarly swapped in the table of Intel Core Microarchitecture.
I take this is an error in the documentation only, and it got
copy-pasted across different CPU family files in the utility.
Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26269
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/msrtool/intel_nehalem.c')
| -rw-r--r-- | util/msrtool/intel_nehalem.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 6f99217f1e..11acdd80d0 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -1657,28 +1657,28 @@ const struct msrdef intel_nehalem_msrs[] = { {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { { BITS_EOT } }}, - {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { { BITS_EOT } }}, - {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { { BITS_EOT } }}, - {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { { BITS_EOT } }}, - {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { { BITS_EOT } }}, {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { |