diff options
author | Victor Ding <victording@google.com> | 2021-02-18 04:27:47 +0000 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-20 09:00:27 +0000 |
commit | 80b2f2358485514cc31da2ee989e928288b80d5c (patch) | |
tree | 27814716b0c5bfd43938c2a188736b2eae3fa24f /util/msrtool/intel_core1.c | |
parent | d4f81bc21d9ffa7d0ef489e8a33ab5155c3b3be1 (diff) |
drivers/generic/bayhub_lv2: move the driver to ".enable"
coreboot sets up certain configs (e.g. L1ss) based on the device's
reported capacities; however, this BayHub lv2 driver modifies some
of its capacities after coreboot uses them. Therefore, coreboot may
make incorrect configs based on out-of-date capacities.
This patch moves the driver from ".init" to ".enable" so that the
capacities are set before the rest of coreboot queries them.
BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" reported "PCI-PM_L1.2-" and "ASPM_L1.2-" on L1SubCtl1
of both PCI device "00:01.3" and "02.00.0"
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I857b7c7c6732bbd26de561052affa3a3e7e25737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util/msrtool/intel_core1.c')
0 files changed, 0 insertions, 0 deletions