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authorEdward O'Callaghan <quasisec@google.com>2020-06-22 12:00:51 +1000
committerEdward O'Callaghan <quasisec@chromium.org>2020-06-23 01:15:14 +0000
commit5d33d03d3f85ec3298a29940417547548b1fd066 (patch)
treedaadf08d80d3eaa49601251b0f66f3bc25572210 /util/mainboard
parentb6737fc54a7fcbcef0af5a1ebbacd97a32ee811a (diff)
util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports
Switch USB2 port1 and port3 due to circuit change from rev0. BUG=b:154071868,b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'util/mainboard')
-rw-r--r--util/mainboard/google/puff/template/overridetree.cb17
1 files changed, 7 insertions, 10 deletions
diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb
index ededac42ed..55ce5ea084 100644
--- a/util/mainboard/google/puff/template/overridetree.cb
+++ b/util/mainboard/google/puff/template/overridetree.cb
@@ -21,9 +21,6 @@ chip soc/intel/cannonlake
}"
# USB configuration
- # NOTE: This only applies to Puff,
- # usb2_ports[1] and usb2_ports[3] were swapped on
- # reference schematics after Puff has been built.
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC2,
@@ -32,23 +29,23 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port 2
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
- register "usb2_ports[2]" = "{
+ register "usb2_ports[1]" = "{
.enable = 1,
- .ocpin = OC3,
+ .ocpin = OC1,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
- }" # Type-A Port 3
- register "usb2_ports[3]" = "{
+ }" # Type-A Port 1
+ register "usb2_ports[2]" = "{
.enable = 1,
- .ocpin = OC1,
+ .ocpin = OC3,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
- }" # Type-A Port 1
+ }" # Type-A Port 3
+ register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[4]" = "{
.enable = 1,
.ocpin = OC_SKIP,